AMD Zen 4 will take advantage of up to 12 DDR5 channels

AMD has released a series of patches for the Error Detection and Correction (EDAC) driver for the next generation EPYC processors based on the Zen 4 microarchitecture. The new patches indicate that upcoming CPUs will support unprecedented memory bandwidth and per-socket capacity.

The patches (as reported by Phoronix colleagues) provide support for Registered DIMM DDR5 (RDIMM) and DIMM load- reduced DDR5 (LRDIMM) for 4th generation EPYC processors codenamed Genoa (models 10h-1Fh and A0h-AFh of the 19h family). The patches also confirm that the EPYC 7004 series will support up to 12 memory controllers per socket, doubling the current eight. Unfortunately, we don't know how many DIMMs per channel (DPC) the chips will support.

Twelve channels of 64bit DDR5 memory would theoretically increase the available bandwidth for Genoa processors to a whopping 460.8GB / s per socket. a significant increase over the 204.8GB / s available for the latest generation EPYC CPUs with DDR4-3200. Memory bandwidth alone will not be the only improvement introduced by the next generation EPYC 'Genoa' CPUs: twelve memory channels will also allow higher capacities for the new processors. Samsung has already shown 512GB DDR5 RDIMMs and confirmed that 768GB DDR5 RDIMMs can be made. Even using 12 512GB modules, AMD's next-generation server processors could support up to 6TB of memory (compared to 4TB today).

Photo Credit: G.Skill However, if Genoa supports two RDIMMs per channel, that capacity will extend up to 12TB. AMD may further increase capacity per memory channel and per socket with LRDIMMs, albeit at the expense of performance. AMD's EPYC 7004 series “Genoa” processors will bring tangible memory improvements over existing server processors, which will naturally improve their performance in the real world.