AMD Ryzen 4000, the first information appears on the net
While we await the official presentation regarding the new processors based on AMD's Zen 3 architecture which will be held on October 8th, the CyberPunkCat leaker has shared some rather interesting details.
The document, which dates back to June 10, seems to come directly from AMD but, even if the information appears to be quite truthful, we will have to wait a few more weeks to confirm this.
With this in mind, the document is a PPR (Processor Programming Reference) guide for AMD Family 19h Model 21h B0. Recall that Zen (+) and Zen 2 belong to the 17h Family, so the 19h Family should be Zen 3.
Unsurprisingly, the AMD Ryzen 4000 series processors (codenamed Vermeer) will retain the multi module design -chip (MCM), otherwise known as a chiplet design. Zen 3 will contain two core complex dies (CCDs) with one I / O die (IOD) within a single package. From the outside the configuration looks identical to Zen 2, but it is not.
On Zen 2, each CCD houses two core complexes (CCX), where each of the latter is composed of four cores that share 16MB of L3 cache. According to the AMD document, the composition of Zen 3 is completely different: there is only one CCX inside each CCD. The CCX has eight cores that can run in single-threaded mode (1T) or in two-threaded SMT mode (simultaneous multithreading) (2T), for a total of 16 threads per core complex. Since only one CCX is now available, all eight CPU cores can directly access 32MB of shared L3 cache.
The document, which dates back to June 10, seems to come directly from AMD but, even if the information appears to be quite truthful, we will have to wait a few more weeks to confirm this.
With this in mind, the document is a PPR (Processor Programming Reference) guide for AMD Family 19h Model 21h B0. Recall that Zen (+) and Zen 2 belong to the 17h Family, so the 19h Family should be Zen 3.
Unsurprisingly, the AMD Ryzen 4000 series processors (codenamed Vermeer) will retain the multi module design -chip (MCM), otherwise known as a chiplet design. Zen 3 will contain two core complex dies (CCDs) with one I / O die (IOD) within a single package. From the outside the configuration looks identical to Zen 2, but it is not.
On Zen 2, each CCD houses two core complexes (CCX), where each of the latter is composed of four cores that share 16MB of L3 cache. According to the AMD document, the composition of Zen 3 is completely different: there is only one CCX inside each CCD. The CCX has eight cores that can run in single-threaded mode (1T) or in two-threaded SMT mode (simultaneous multithreading) (2T), for a total of 16 threads per core complex. Since only one CCX is now available, all eight CPU cores can directly access 32MB of shared L3 cache.