Intel is already working on 3D stacking after Foveros

During the recent Architecture Day 2020, Intel presented its projects related to the next technologies that it will use for packaging and chip stacking, which will allow to increase the number of connections between the various parts of the processors, thus maximizing the bandwidth and reducing latency, even between layers that have been made with different manufacturing processes.

The Santa Clara company has devised its own physical interconnection topology, Embedded Multi-Die Interconnect Bridge (EMIB), which allows 2D expansion and Foveros 3D die-to-die stacking for vertical expansion. However, this system will be supplanted in the future by “Hybrid Bonding”, which Intel will use to increase the number of bump densities by a factor of 3-10 over previous technologies. Early test chips used this approach with SRAM, reaching 10,000 bumps per mm², with less than 0.05 picojoules per bit required power. According to Intel, this will allow for smaller and simpler circuits with lower consumption and significantly increased efficiency.

All these technologies will also be used to better manage temperatures and, according to the company, it will be necessary to design all the various layers together, and not independently, to perfectly match their electrical and thermal characteristics, to the advantage of energy absorption and reliability.